The prior art has a multitude of single-port single-bank DRAM memory chips and of memory configurations of such memory chips in single-port and multiple-port arrangements. However, the prior art is not known to disclose any single chip architecture for structuring a single DRAM semiconductor chip with multiple ports and multiple DRAM banks--which is the primary object of the subject invention. A clear distinction needs to be made between different types of memory chips.
For example, U.S. Pat. No. 4,745,545 shows a memory using memory banks which "the memory banks are organized into each section of memory in a sequential and interleaved fashion", which is not the way the internals of the subject invention are organized (and in which it is believed that each memory bank may be a separate chip). U.S. Pat. No. 4,745,545 focuses on having unidirectional ports (read or write), and on conflict resolution among its ports, and on supporting an interleaved memory for multiple processor accesses, which is not a focus within the chip of the subject invention which does not have unidrectional ports.